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vishay siliconix dg417b, dg418b, dg419b document number: 72107 s09-1261-rev. d, 13-jul-09 www.vishay.com 1 precision monolithic quad spst cmos analog switches description the dg417b, dg418b, dg419b monolithic cmos analog switches were designed to provide high performance switching of analog signals. combining low power, low leakages, high speed, low on-resistance and small physical size, the dg417b series is ideally suited for portable and battery powered industrial and military applications requiring high performance and efficient use of board space. to achieve high-voltage ratings and superior switching performance, the dg417b se ries is built on vishay siliconix?s high voltage silicon gate (hvsg) process. break- before-make is guaranteed for the dg419b, which is an spdt configuration. an epit axial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. the dg417b and dg418b respond to opposite control logic levels as shown in the truth table. features ? 15 v analog signal range ? on-resistance - r ds(on) : 15 ? fast switching action - t on : 110 ns ? ttl and cmos compatible ? msop-8 and soic-8 package ? compliant to rohs directive 2002/95/ec benefits ? widest dynamic range ? low signal errors and distortion ? break-before-make switching action ? simple interfacing ? reduced board space ? improved reliability applications ? precision test equipment ? precision instrumentation ? battery powered systems ? sample-and-hold circuits ? military radios ? guidance and control systems ? hard disk drivers functional block diagram and pin configuration logic "0" 0.8 v logic "1" 2.4 v logic "0" 0.8 v logic "1" 2.4 v * pb containing terminations are not rohs compliant, exemptions may apply 1 d u al-in-line, soic- 8 and msop- 8 s d v - g n d i n v + v l 2 3 4 8 7 6 5 to p v ie w d g 417b n o connect truth table logic dg417b dg418b 0 on off 1offon 1 d u al-in-line, soic- 8 and msop- 8 ds 2 s 1 v - g n di n v + v l 2 3 4 8 7 6 5 top v ie w dg419b truth table - dg419b logic sw 1 sw 2 0 on off 1offon
www.vishay.com 2 document number: 72107 s09-1261-rev. d, 13-jul-09 vishay siliconix dg417b, dg418b, dg419b notes: a. signals on s x , d x , or in x exceeding v+ or v- will be clamped by internal diodes . limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 5.3 mw/c above 75 c. d. derate 4 mw/c above 70 c. e. derate 8 mw/c above 75 c. ordering information temp range package part number dg417b, dg418b - 40 c to 85 c 8-pin plastic minidip dg417bdj dg417bdj-e3 dg418bdj dg418bdj-e3 8-pin narrow soic dg417bdy dg417bdy-e3 dg417bdy-t1 dg417bdy-t1-e3 dg418bdy dg418bdy-e3 dg418bdy-t1 dg418bdy-t1-e3 8-pin msop dg417bdq-t1-e3 dg418bdq-t1-e3 dg419b - 40 c to 85 c 8-pin plastic minidip dg419bdj DG419BDJ-E3 8-pin narrow soic dg419bdy dg419bdy-e3 dg419bdy-t1 dg419bdy-t1-e3 8-pin msop dg419bdq-t1-e3 absolute maximum ratings parameter limit unit v- - 20 v v+ 20 gnd 25 v l (gnd - 0.3) to (v+) + 0.3 digital inputs a , v s , v d (v-) - 2 v to (v+) + 2 or 30 ma, whichever occurs first current, (any terminal) continuous 30 ma current (s or d) pulsed at 1 ms, 10 % duty cycle 100 storage temperature - 65 to 150 c power dissipation (package) b 8-pin plastic minidip c 400 mw 8-pin narrow soic c 400 8-pin msop d 400 8-pin cerdip e 600
document number: 72107 s09-1261-rev. d, 13-jul-09 www.vishay.com 3 vishay siliconix dg417b, dg418b, dg419b schematic diagram typical channel figure 1. le v el shift/ dri v e v i n v l s v + g n d v - d v - v + specifications a parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full - 15 15 - 15 15 v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 12.5 v v+ = 13.5 v, v- = - 13.5 v room full 15 25 34 25 29 switch off leakage current i s(off) v+ = 16.5, v- = - 16.5 v v d = 15.5 v, v s = 15.5 v room full - 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 na i d(off) dg417b dg418b room full - 0.1 - 0.25 - 20 0.25 20 - 0.25 - 5 0.25 5 dg419b room full - 0.1 - 0.75 - 60 0.75 60 - 0.75 - 12 0.75 12 channel on leakage current i d(on) v+ = 16.5 v, v- = - 16.5 v v s = v d = 15.5 v dg417b dg418b room full - 0.4 - 0.4 - 40 0.4 40 - 0.4 - 10 0.4 10 dg419b room full - 0.4 - 0.75 - 60 0.75 60 - 0.75 - 12 0.75 12 digital control input current, v in low i il full - 0.5 0.5 - 0.5 0.5 a input current, v in high i ih full - 0.5 0.5 - 0.5 0.5 dynamic characteristics tu r n - o n t i m e t on r l = 300 , c l = 35 pf v s = 10 v, see switching time test circuit dg417b dg418b room full 62 89 106 89 99 ns turn-off time t off dg417b dg418b room full 53 80 88 80 86 transition time t trans r l = 300 , c l = 35 pf v s1 = 10 v, v s2 = 10 v dg419b room full 60 87 96 87 93 break-before-make time delay t d r l = 300 , c l = 35 pf v s1 = v s2 = 10 v dg419b room 16 3 3 charge injection q c l = 10 nf v gen = 0 v, r gen = 0 room 38 pc off isolation e oirr r l = 50 , c l = 5 pf, f = 1 mhz room - 82 db channel-to-channel crosstalk e x ta l k dg419b room - 88
www.vishay.com 4 document number: 72107 s09-1261-rev. d, 13-jul-09 vishay siliconix dg417b, dg418b, dg419b notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this datas heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol test conditions unless otherwise specified v+ = 15 v, v- = - 15 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max d. dynamic characteristics source off capacitance e c s(off) f = 1 mhz, v s = 0 v room 12 pf drain off capacitance e c d(off) dg417b dg418b room 12 channel on capacitance e c d(on) f = 1 mhz, v s = 0 v dg417b dg418b room 50 dg419b room 57 power supplies positive supply current i+ v+ = 16.5 v, v- = - 16.5 v v in = 0 or 5 v room full 0.001 1 5 1 5 a negative supply current i- room full - 0.001 - 1 - 5 - 1 - 5 logic supply current i l room full 0.001 1 5 1 5 ground current i gnd room full - 0.001 - 1 - 5 - 1 - 5 specifications a parameter symbol test conditions unless otherwise specified v+ = 12 v, v- = 0 v v l = 5 v, v in = 2.4 v, 0.8 v f temp. b typ. c a suffix - 55 c to 125 c d suffix - 40 c to 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 12 0 12 v drain-source on-resistance r ds(on) i s = - 10 ma, v d = 3.8 v v+ = 10.8 v room full 26 35 52 35 45 dynamic characteristics tu r n - o n t i m e t on r l = 300 , c l = 35 pf v s = 8 v, see switching time test circuit room full 100 125 155 125 143 ns turn-off time t off room full 38 66 73 66 69 break-before-make time delay t d r l = 300 , c l = 35 pf dg419b room 62 25 25 transition time t trans r l = 300 , c l = 35 pf v s1 = 0 v, 8 v, v s2 = 8 v, 0 v room full 95 119 153 119 141 charge injection q c l = 10 nf, v gen = 0 v, r gen = 0 room 18 pc power supplies positive supply current i+ v+ = 13.2 v, v l = 5.25 v v in = 0 or 5 v room full 0.001 1 5 1 5 a negative supply current i- room - 0.001 - 1 - 5 - 1 - 5 logic supply current i l room 0.001 1 5 1 5 ground current i gnd room - 0.001 - 1 - 5 -1 - 5 specifications a
document number: 72107 s09-1261-rev. d, 13-jul-09 www.vishay.com 5 vishay siliconix dg417b, dg418b, dg419b typical characteristics t a = 25 c, unless otherwise noted on-resistance vs. v d and unipolar power supply voltage on-resistance vs. v d and temperature leakage vs. analog voltage 0 50 100 150 200 250 300 04 8 12 16 20 v + = 3 v v l = 3 v v + = 5 v t a = 25 c v l = 5 v r ds(on) - ( ) e c n a t s i s e r - n o e c r u o s - n i a r d v d - drain v oltage ( v ) v + = 8 v v + = 12 v v + = 15 v v + = 20 v 5 10 15 20 25 30 - 15 - 10 - 5 0 5 10 15 - 55 c v = 15 v v l = 5 v 25 c 8 5 c r ds(on) - ( ) e c n a t s i s e r - n o e c r u o s - n i a r d v d - drain v oltage ( v ) 125 c - 100 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 -15 - 10 - 5 0 5 10 15 v d or v s - drain or so u rce v oltage ( v ) v = 15 v v l = 5 v t a = 25 c i d i , s ) a p ( i s(off) i d(off) i d(on) on-resistance vs. v d and dual supply voltage on-resistance vs. v d and temperature supply current vs. input switching frequency 5 10 15 20 25 30 35 40 - 20 - 15 - 10 - 5 0 5 10 15 20 e ( ) c n a t s i s e r - n o e c r u o s - n i a r r ds(on) - d v d - drain v oltage ( v ) t a = 25 c 5 v 8 v 10 v 15 v 20 v 12 v 5 10 15 20 25 30 35 40 45 5 0 0246 8 10 12 - 55 c 25 c 8 5 c r ds(on) - ( ) e c n a t s i s e r - n o e c r u o s - n i a r d v d - drain v oltage ( v ) 125 c v + = 12 v v - = 0 v v l = 5 v inp u t s w itchin g fre qu ency (hz) 10 100 1 k 10 k 100 k 1 m 10 m 100 p 10 n 100 n 1 m 100 m 1 10 100 ) a n ( t n e r r u c y l p p u s + - i 10 m 1 n v = 15 v v l = 5 v i l i+, i-
www.vishay.com 6 document number: 72107 s09-1261-rev. d, 13-jul-09 vishay siliconix dg417b, dg418b, dg419b typical characteristics t a = 25 c, unless otherwise noted switching time vs. temperature transition time vs. temperature switching threshold vs. supply voltage ) s n ( 20 40 60 8 0 100 120 140 - 55 - 35 - 15 5 25 45 65 8 5 105 125 t n o t , f f o temperat u re ( c) t off v = 12 v t o n v = 15 v t o n v = 12 v v l = 5 v t off v = 15 v 20 40 60 8 0 100 120 140 - 55 - 35 - 15 5 25 45 65 8 5 105 125 te m p erat u re ( c ) ) s n ( t n o t , f f o v + = 12 v v - = 0 v v l = 5 v t tra n s+ t tra n s- 0.0 0.5 1.0 1.5 2.0 2.5 3 . 0 46 8 10 12 14 16 1 8 20 ) v ( d l o h s e r h t g n i h c t i w s v + - s u pply v oltage ( v ) v t - v l = 5 v transition time vs. temperature insertion loss, off -isolati on crosstalk vs. frequency insertion loss, off -isolati on crosstalk vs. frequency 20 30 40 50 60 70 8 0 90 100 - 55 - 35 - 15 5 25 45 65 8 5 105 125 te m p erat u re ( c ) t tra n s- v = 15 v v l = 5 v t tra n s+ ) s n ( t n o t , f f o k l a t fre qu ency (hz) ) b d ( x , r r i o , s s o l - 100 - 90 - 8 0 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 100k 1m 10m 100m 1g oirr loss dg417b v + = + 15 v v - = - 15 v r l = 50 k l a t fre qu ency (hz) ) b d ( x , r r i o , s s o l - 100 - 90 - 8 0 - 70 - 60 - 50 - 40 - 30 - 20 - 10 0 10 100k 1m 10m 100m 1g loss x talk dg419b v + = + 15 v v - = - 15 v r l = 50 oirr
document number: 72107 s09-1261-rev. d, 13-jul-09 www.vishay.com 7 vishay siliconix dg417b, dg418b, dg419b typical characteristics t a = 25 c, unless otherwise noted test circuits charge injection vs. analog voltage (measured at drain pin) charge injection vs. analog voltage (measured at drain pin) analog v oltage ( v ) q inj - charge injection (pc) - 100 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 1 8 0 200 - 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15 v + = + 12 v v - = 0 v v + = + 12 v v - = - 12 v v + = + 15 v v - = - 15 v dg417b c l =10nf analog v oltage ( v ) q inj - charge injection (pc) - 200 - 1 8 0 - 160 - 140 - 120 - 100 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 - 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15 v +=+12 v v -=-0 v dg419b c l =10nf v +=+15 v v -=-15 v v +=+12 v v -=-12 v charge injection vs. analog voltage (measured at source pin) charge injection vs. analog voltage (measured at source pin) q inj - charge injection (pc) v + = + 15 v v - = - 15 v v + = + 12 v v - = 0 v v + = + 12 v v - = - 12 v dg417b c l =10nf - 100 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 1 8 0 200 - 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15 analog v oltage ( v ) analog v oltage ( v ) q inj - charge injection (pc) - 100 - 8 0 - 60 - 40 - 20 0 20 40 60 8 0 100 120 140 160 1 8 0 200 - 15 - 12 - 9 - 6 - 3 0 3 6 9 12 15 v +=+12 v v -=-0 v dg419b c l =10nf v +=+15 v v -=-15 v v +=+12 v v -=-12 v figure 2. switching time (dg417b/418b) c l (incl u des fixt u re and stray capacitance) r l r l + r ds(on) v o = v s v - i n s d c l 35 pf - 15 v v l g n d v o 10 v v + r l 300 + 15 v + 5 v v o is the steady state o u tp u t w ith the s w itch on. 0 v logic inp u t s w itch inp u t s w itch o u tp u t 3 v 50 % 0 v v o v s t r < 5 ns t f < 5 ns t off t o n 90 % n ote: logic inp u t w a v eform is in v erted for s w itches that ha v e the opposite logic sense.
www.vishay.com 8 document number: 72107 s09-1261-rev. d, 13-jul-09 vishay siliconix dg417b, dg418b, dg419b test circuits figure 3. break-before-make (dg419b) i n v l v s1 d v - v s2 s 2 v + s 1 - 15 v g n d + 1 v + 5 v c l 35 pf v o r l 300 c l (incl u des fixt u re and stray capacitance) 0 v 3 v 0 v logic inp u t s w itch o u tp u t v o v s1 = v s2 t r < 5 ns t f < 5 ns 90 % t d t d figure 4. transition time (dg419b) c l (incl u des fixt u re and stray capacitance) v l r l r l + r ds(on) v o = v s v - v + i n c l 35 pf r l 300 d v o s 2 s 1 v s2 v s1 - 15 v g n d + 15 v + 5 v 0 v 3 v 50 % logic inp u t s w itch o u tp u t v s1 t r < 5 ns t f < 5 ns 10 % t tra n s 90 % v 01 v s2 v 02 t tra n s figure 5. charge injection c l 10 nf d r g v o v + s v - 3 v i n v l - 15 v g n d + 15 v + 5 v off o n off v o v o i n x q = v o x c l
document number: 72107 s09-1261-rev. d, 13-jul-09 www.vishay.com 9 vishay siliconix dg417b, dg418b, dg419b test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72107 . figure 6. crosstalk r g = 50 i n 0. 8 v v l v + v - x talk isolation = 20 log v o v s g n d s 2 v s v o s 1 r l d c = rf b ypass 50 + 15 v - 15 v c c + 5 v c figure 7. off isolation v + s v l r g = 50 d - 15 v v s g n d v - c r l i n v o 0 v , 2.4 v off isolation = 20 log v o v s + 5 v c + 15 v c figure 8. insertion loss s v s v o 0 v , 2.4 v i n r l v l d r g = 50 + 5 v - 15 v g n d v - c c + 15 v v + c figure 9. source/drain capacitances v l i n s v + d f = 1 mhz c 0 v , 2.4 v meter hp4192a impedance analyzer or e qu i v alent + 5 v c + 15 v c d 2 d 1 s 1 f = 1 mhz + 15 v i n s 2 n c - 15 v g n d v + c c 0 v , 2.4 v meter hp4192a impedance analyzer or e qu i v alent dg417b/41 8 b dg419b f = 1 mhz - 15 v g n d v - v -
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 71244 12-jul-02 www.vishay.com 1 msop: 8?leads jedec part number: mo-187, (variation aa and ba) n = 8l millimeters dim min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.25 - 0.38 8 b 1 0.25 0.30 0.33 8 c 0.13 - 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.65 bsc e 1 1.95 bsc l 0.40 0.55 0.70 4 n 8 5 0 4 6 ecn: t-02080?rev. c, 15-jul-02 dwg: 5867
q 1 a l a 1 b e 1 e e 1 b 1 s c e a d 15 max 1234 8765 note: end leads may be half leads. package information vishay siliconix document number: 71259 05-jul-01 www.vishay.com 1
dim min max min max a 3.81 5.08 0.150 0.200 a 1 0.38 1.27 0.015 0.050 b 0.38 0.51 0.015 0.020 b 1 0.89 1.65 0.035 0.065 c 0.20 0.30 0.008 0.012 d 9.02 10.92 0.355 0.430 e 7.62 8.26 0.300 0.325 e 1 5.59 7.11 0.220 0.280 e 1 2.29 2.79 0.090 0.110 e a 7.37 7.87 0.290 0.310 l 2.79 3.81 0.110 0.150 q 1 1.27 2.03 0.050 0.080 s 0.76 1.65 0.030 0.065 ecn: s-03946?rev. e, 09-jul-01 dwg: 5478
e 1 e q 1 a l a 1 e 1 b b 1 l 1 s c e a d 1234 8765 package information vishay siliconix document number: 71280 03-jul-01 www.vishay.com 1
dim min max min max a 4.06 5.08 0.160 0.200 a 1 0.51 1.14 0.020 0.045 b 0.38 0.51 0.015 0.020 b 1 1.14 1.65 0.045 0.065 c 0.20 0.30 0.008 0.012 d 9.40 10.16 0.370 0.400 e 7.62 8.26 0.300 0.325 e 1 6.60 7.62 0.260 0.300 e 1 2.54 bsc 0.100 bsc e a 7.62 bsc 0.300 bsc l 3.18 3.81 0.125 0.150 l 1 3.18 5.08 0.150 0.200 q 1 1.27 2.16 0.050 0.085 s 0.64 1.52 0.025 0.060 0 15 0 15 ecn: s-03946?rev. c, 09-jul-01 dwg: 5348
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
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